High speed digital systems, whether for computational or communications purposes, rely on the ability to correctly ascertain the logical value of a binary data signal at specific times. In a digital system there are abrupt transitions between the logical values, and the nominal period of time that the data signal can represent a particular logical value is called the UI (for Unit Interval). Generally, there is provided (or derived) another signal, called a clock signal, whose period is also the UI and whose abrupt transitions in a selected direction serve as the above-mentioned ‘specific times’ at which the logical value of the data signal is to be ascertained, a process which is often termed ‘sampling.’
In an ideal world, all edges in the data signal would occur at locations along a time axis that were an exact UI apart, or at exact multiples of the unit interval. The ‘rattle’ that actually occurs in the edge position of a signal that is supposed to transition only at particular times is timing jitter, and when it is understood that it refers to edges, it is often called simply ‘jitter.’ But the notion of jitter as a succession of incorrect minor errors includes more than timing phenomena; the voltage levels that are asserted to represent the logical values are generally not ideal, either. That is, their voltage levels may vary in time while asserted (and here we are neglecting proper excursions for rise and fall), or exhibit slow drift over time or with temperature. The more rapid variations within a UI (or among a collection of UI occurring at about the same time) while asserted are often thought of as voltage noise, and are also properly thought of as a form of jitter. We are in this Application more interested in the rapid noise behavior than in slow drift, and are prepared to consider such noise as voltage jitter that is also included within the scope of the term ‘jitter.’ Voltage jitter as a form of jitter is perhaps less familiar than the notion of noise (real signal equals ideal signal plus noise of some bandwidth), but is still a useful concept, since it lets us characterize voltage behavior using the jitter analysis tools developed for timing jitter. Voltage jitter can have just as deleterious an effect on ascertaining logical values as timing jitter does, as it lowers margins for logical value determination and, when it affects an edge of finite slope, moves the location of a threshold crossing (should one be in use). Much of what we will say applies to both timing and voltage jitter, and should be understood as such when we use the term ‘jitter’ either in isolation or without a qualifying context. We shall endeavor to indicate which of timing or voltage jitter we have in mind when the topic at hand does not apply to both.
One further clarification is in order. While we recognize that both timing and voltage jitter can affect a system, and that each can be measured, characterized and analyzed through the use of similar techniques and paradigms, we shall treat them as separate phenomena, in that they have separate causes, but which can sometimes produce overlapping results (as when voltage noise moves the location of a threshold crossing). In this view, jitter is only known through measurement, and how it is measured greatly affects the result that is obtained. We remain mindful that when a complex thing is measured two different ways, we must not be surprised if the answers are not identical.
In today's high performance digital systems, the presence of jitter in the data signal or in the clock has a significant effect on the system's ability to correctly ascertain the logical values of the data signal. To reduce jitter one generally has to locate its source, a clue to which is the type of jitter it produces. It turns out that it is useful to recognize that each of overall timing jitter and overall voltage jitter is composed of several different types of (component) jitter. Test equipment intended for use with high performance digital systems often include in their repertoire of operations automated measurements of several types of jitter. Total Jitter (TJ) is the aggregate amount of observable jitter, and is (or ought to be) the ‘sum’ of all the various types of component jitter. Types of component jitter include Periodic Jitter (PJ), Random Jitter (RJ) and Data Dependent Jitter (DDJ). DDJ is jitter that is correlated with the content of the data itself. It is generally not possible to readily directly measure only a particular type of component jitter, since we can't observe those types in isolation: the measured data will generally include the combined effects of various types of jitter. Indirect methods are needed to separate from a combined result the data for an individual type of jitter (e.g., using a suitable models or other analysis technique).
That said, one thing we won't attempt is the wholesale decomposition of one kind of timing jitter into some equivalent form of voltage jitter, or vice versa. (It might work sometimes, but not always.) Like different genders, sometimes what they do overlaps, and they have things in common. Yet it appears that the most practical approach is to say that timing jitter is one way of measuring something, and that voltage jitter is another way, and that while both are measurements of jitter, the ultimate causes of that jitter are varied. Some are specific to voltages and others to timing, while some might be thought of as causing both. So, when we offer an analysis of, say, a particular measured (timing) component jitter for TJ (for timing), it will be appreciated that, unless otherwise stated, there is a corresponding (voltage) measured component jitter for voltage TJ, but that the two TJs and their respective components are treated as though they were quite distinct from one another.
(Upon reflection, one might wonder if the two measured types of TJ combine to indicate more jitter than is ‘actually’ there. That does seem to be a possibility, since one or more causes may be contributing twice. However, we are NOT tempted to combine the two measurements, nor do we have a way to measure any supposed ‘real’ Total Jitter. To be sure, we can get a voltage waveform that has been sampled as densely as you'd like and that ought to be an operationally complete description of ‘real’ Total Jitter—but then what? What is the rule for putting this behavior into this bin and that behavior into another. And if no such separation is attempted, then what is the unit of measure by which the jitter is to be described in the first place? (Evidently the unit is not simply one of time or voltage . . . ) Well, one might imagine the integral of the difference between an ideal waveform and the real one, divided by time. It is a unified measure and essentially it is an area. So, say we give you one hundred square feet of some stuff, the value or usefulness of which may well be different if it is a sheet ten feet by ten feet, as opposed to one foot by a hundred feet. The dimensions of the area influence your opinion of the circumstances. So it is with waveforms; both voltage and time are independently important, even though they might be combined into an ‘area’ that is the product of two dimensions. It seems we are stuck with measuring the jitter of each of the time and voltage dimensions, even though those dimensions don't always have independent causes for their jitter.)
We are particularly interested here in a DDJ measurement technique for both timing and voltage jitter that is useable in a real time Digital Sampling Oscilloscope (DSO) or comparable environment. It begins with the production of a suitably long digital Test Pattern which may contain a random sequence of bit values, or, which might be actual live data. An Acquisition Record is made of the entire Test Pattern. (That is to say, the digital data may be sampled using the techniques found in modem high speed real time DSOs, in which case a representation (a sequence of numbers in a file) of the actual analog waveform of the sampled digital signal is reconstructed with Digital Signal Processing (DSP) techniques, and the sequence of logical values found from inspection of that reconstruction. What follows for the next several paragraphs is a highly abbreviated version of the Summary of the incorporated METHOD OF FINDING DATA DEPENDENT TIMING AND VOLTAGE JITTER IN AN ARBITRARY DIGITAL SIGNAL IN ACCORDANCE WITH SELECTED SURROUNDING BITS. Our immediate aim in the next several paragraphs is to support the notion that we can get both a UI by UI (for voltage) and edge-by-edge (for timing) description of DDJ.
For timing jitter measurements, an original Time Interval Error (TIE) Record is made from an inspection of the locations of the edges in the Acquisition Record. (A TIE Record is a data structure that associates, for each edge in the Acquisition Record, the error in time by which that edge actually transitioned, as opposed to when it should have.) This may be accomplished with the help of an associated clock signal that either accompanies the data signal of interest or that is derived therefrom.
For a voltage jitter measurement, an original Voltage Level Error (VLE) Record is made from an inspection of the behavior of the signal at locations within the exerted but non-transition portions of each UI. A VLE Record is similar to a TIE Record, except that it is, for each UI, an aggregate measure of how the asserted voltage varies from the ideal case. Upon reflection, it will be appreciated that such a measure is, of necessity, somewhat stylized, in that one might obtain such a measure in any of several different ways, and that each will likely produce a somewhat different result. (For example: How much of the interior of the UI is inspected? Are RMS values used or just peak-to-peak excursions? And so on.) The answer is that all these different approaches are valid, and it is principally a question of cost versus benefit influenced by preference combined with available resources. Upon further reflection, it will be realized that a similar can of worms is associated with the seemingly simpler task of finding Time Interval Error values from when in time the signal actually crossed a threshold. (For example, DSP can convert sampled values to a dense time domain collection of sequential voltage values, but where is the threshold supposedly set? Is it an absolute value? Is it some sort of weighted average? Or is it a simple average of peak logic level excursions? And is straight-line interpolation sufficient to find the actual threshold crossing when—as usually occurs—the values provided by the DSP fall on either side of the threshold, or is a curve fit appropriate?) Once again, the answer is that all these different approaches are valid, and it is principally a question of cost, benefit and preference combined with available resources.
Fortunately, all these considerations about how to find a TIE or VLE value are applicable as post-data-acquisition processing activities, so that if it takes a few seconds to apply the selected techniques to the Acquisition Record, that won't be a burden. (That is, as long as we don't have to do it in real time at a rate fast enough to keep up with the data . . . .) And, if we have confidence in the DDJ measurements that result (and we haven't described yet how those are accomplished), then we really need to do that original TIE/VLE Record production only once for a suitable Test Pattern, as subsequent ‘live’ data can be processed for DDJ much more quickly if the following assumption is true: Suppose we found the TIE/VLE Records for that subsequent ‘live’ data—they won't be significantly different than the ones we already found for the Test Pattern, so we can continue to use an existing earlier found understanding of DDJ for the particular SUT of interest.
To continue with DDJ measurements, a user defines a Template that is a collection of associated bit behaviors at bit locations that are nearby or otherwise related to a (reference) bit location of interest. The locations within the collection need not be contiguous or adjacent. A Template can be defined as either bit values, as transitions (edges), or as a mixture of both. A Template might be the two bit-values (or transitions) before and the two bit-values (or transitions) after the bit value (or transition) of interest. The nature of the expected source of jitter may influence the nature of the Template. For example, an electrical structure involving a transmission line that is causing reflections might prompt the use of a Template having two or more groups of one or several bits in each group, where the groups are separated by a number of bit positions.
A Template has associated therewith a collection of Descriptors and their respective Metrics. Each Descriptor identifies an instance of the various different patterns of bit values (or transitions) that, if they were to occur, would fit the Template. For example, the ‘two before/at/two after’ bit-value Template can have (at most) thirty-two different ways that it can occur (‘two before’ plus ‘two after’ plus the one of interest that is ‘at’ is five two-valued bits, for 25=32 different patterns, although the need for an ‘at’ edge to occur will cut the number of possible Descriptors in half). The DSP reconstruction (Acquisition Record) of the actual waveform of the Test Pattern is examined (in conjunction with the original TIE Record and/or perhaps the original VLE Record) for the presence of Descriptors. The signed amount of TIE/VLE for the bit position of interest (in the Template) that locates the position of any Descriptor anywhere along the waveform is measured from the original TIE/VLE Record, for each occurring instance of each Descriptor in the Template. The collection of measured TIE/VLE values for each particular Descriptor are averaged (or otherwise combined) to produce a DDJ Metric for that Descriptor. A Look-Up Table (LUT) addressed by the different possible Descriptors is loaded with the discovered DDJ Metric that is associated with each Descriptor.
Such a LUT can be used to separate TJ into one portion that is DDJ and into another portion that is PJ convolved with RJ. The separation works because: (1) TJ is assumed to be the ‘sum’ of those two portions and no others; and (2) DDJ is correlated with the Descriptors, while PJ and RJ (and thus also their convolution) can be expected to average to nearly zero (‘self-cancellation’) over a sufficient number of instances of a given Descriptor; i.e., if the Test Pattern is long compared to the size of the Template. Once that LUT is created a plausible value of DDJ can be imputed to each UI (voltage jitter)/edge (timing jitter) in the test pattern by using the Descriptor associated with that UI/edge as an index to address the LUT and obtain the DDJ Metric stored therein.
Now, supposing that we have in hand such a precise description of DDJ occurring in a System Under Test (SUT), there are various ways that it might be put to good use. As an example, the identified instances of DDJ can then be individually removed from the corresponding locations of the Original TIE Record for the measured TJ to produce an Adjusted TIE Record whose only remaining jitter is PJ convolved with RJ. Down that path lies a further analysis of those types of jitter. Another example is the discovery of a filter for regular use on actual data to remove or lessen the effects of that DDJ. The data resulting from such filtering is often referred to as having been ‘equalized’ and the filtering process itself called ‘equalization.’ It is a form of error reduction, and it is to the support of such equalization that this Application is principally directed.
Certainly, if one were to include such an equalization mechanism in a data communications path he would like to be able to test it under varying conditions, or, use an obtained description of the DDJ it is suppose to fix as a way to arrive at a corresponding definition of the filter. We have just seen that a description of DDJ can be found, and we will assume that given that description competent engineering efforts can arrive at a proposal for an equalization filter. But how well will it work? And what will be the effects of including other types of jitter in the data? Such questions are often answered with a fairly good degree of certainty before any proposed design is committed to silicon, as it were, by sophisticated modeling techniques performed using computers. That is, there are computer programs that use as data a suitably dense time domain description of an input waveform (akin to our Acquisition Record) and apply that to an emulation of the proposed system (a ‘virtual SUT,’ as it were) to see what happens. A virtual SUT may very well include a proposed equalization scheme in need of characterization. To test the virtual SUT we need to send it particular kinds of data, in order to judge its performance.
For example, one might half-split the virtual SUT into a first portion that is the equalization filter and a second portion that is whatever follows. Equalized data (with and without non-DDJ jitter) could then be sent to the second portion to characterize its behavior. And, even before deciding upon an equalization scheme, it would be nice to have good confidence that removal of the associated DDJ will produce a satisfactory result that is worth the effort. In support of that last idea, a sequential record of values representing a non-equalized waveform for the data, including jitter, can be applied to a mechanism that produces an eye diagram. Say, for example, the aforementioned Original Acquisition Record is used for that purpose. Then a similar Equalized Acquisition Record is applied, and any improvement in the eye diagram is noted and considered. If the eye diagram is already pretty good and does not get much better, then we are invited to decide if equalization is worth the trouble, or, if the eye diagram is marginal and stays that way, perhaps our present description of DDJ for the SUT is inadequate. That is, if there is not sufficient improvement for a ratty looking eye diagram, maybe we should try a more complex Template for DDJ, and do so BEFORE we commit resources to developing an equalization filter based on the discovered DDJ associated with that (suspect) Template. A third case is that a marginal eye diagram gets significantly better when DDJ is removed. Then we know that it is indeed worth the trouble to perform equalization, and also know what equalization to perform. We can also use such experimentation to ensure that we do not inadvertently use a Template that is more complex than needed, by trying increasingly more complex Templates and noting at what point an ‘improved’ understanding of DDJ fails to provide increased eye openings (i.e., this more complex equalization is not significantly better than this simpler one).
Now, how such models for virtual SUTs and eye diagram analyzers driven from data in a file actually work internally is not our present interest; that they do work is a matter of record supported by their presence in commerce. But how to convert our Original Acquisition Record into appropriate Equalized Acquisition Records for use as input for testing by such mechanisms is a set of interesting problems. Equalization of timing jitter or equalization of voltage jitter can each be performed as a sole type of equalization, and a technique is needed for each. An eye diagram evaluation could reveal that one or the other equalization has a pronounced effect, or has almost no effect. But as will become clear in due course, when both are used together, they interact. We can assess the consequences of such interaction if we create an Equalized Acquisition Record that mimics the interaction and then evaluate the result with an eye diagram. This could help us decide that we want a combined equalization scheme that uses more of one type and less of the other. How to model that interaction is yet another interesting problem.
So, we have issues concerning DDJ Template verification, DDJ equalization benefit verification, and concerning interaction between voltage and timing types of equalization for DDJ. All in all, quite a nice little nest of snakes. It would appear that suitable Equalized Acquisition Records would, if we but had them, give us a useful snake abatement tool. Currently, we have no such Equalized Acquisition Records, and after some thought we realize that any attempt to make them runs certain risks. A ‘meat cleaver’ cut and paste approach to moving edges for timing jitter reduction, for instance, may introduce apparent (and spurious) voltage discontinuities in the equalized waveform. We seek a genuine reduction in the magnitude of the snake situation, and not merely an exchange of one snake for another. Apparently, some sophistication is required in the creation of such Equalized Acquisition Records. What to do?